The present invention relates to a semiconductor memory device for storing desired data therein and performing reading or writing of data therefrom and thereto at high speed.
Among various kinds of semiconductor memory devices, dynamic random access memory (hereinafter referred to as DRAM) has been often used as a mass storage device.
Referring to FIGS. 1, 12 and 13, a DRAM of Conventional Example 1 will be explained.
FIG. 1 shows the structure of the DRAM of Conventional Example 1 in schematic form. (FIG. 1 also applies to Embodiments.)
The DRAM will be described below with reference to FIG. 1.
The DRAM as shown in FIG. 1 has a memory subarray 1, a sense amplifier subarray 2, a peripheral circuit area 3, a write-only data bus 4 and a read-only data bus 5.
In the memory subarray 1, a plurality of DRAM cells is arranged in an array. In the sense amplifier subarray 2, a plurality of sense amplifier for detecting and amplifying a small signal of the memory subarray 1 is arranged in an array. The peripheral circuit area 3 receives or sends data from/to outside. The write-only data bus 4 transfers data from the peripheral circuit area 3 to a memory cell via the sense amplifier. The read-only data bus 5 transfers data in a memory cell amplified by the sense amplifier to the peripheral circuit area 3.
Operations of the conventional DRAM thus constructed will be described below.
In writing data from outside into a memory cell, the data from the peripheral circuit area 3 is written into the sense amplifier subarray 2 through the write-only data bus 4 and then the data in the sense amplifier subarray 2 is written into a designated memory cell through a bit line.
In reading data to outside, data in a memory cell is amplified by the sense amplifier subarray 2 via a bit line and then the amplified data is transferred to the peripheral circuit area 3 through the read-only data bus 5 to read out.
FIG. 12 is a schematic view illustrating data buses formed on the memory subarray of the semiconductor memory device according to Conventional Example 1 (when viewed from a top surface of the semiconductor memory device). In FIG. 12, reference numerals 1, 4 and 5 designate the memory subarray, the write-only data bus and the read-only data bus, respectively. The functions of these elements are mentioned above.
FIG. 13 is a schematic sectional view illustrating wiring of data buses of the semiconductor memory device according to Conventional Example 1 (a sectional view taken along the face perpendicular to each data bus line on the memory array (the face Vxe2x80x94V of FIG. 12)).
In the present specification (including each Conventional Example and Embodiment), RDB1, XRDB1, RDB2, XRDB2, RDB3 and so forth are read lines, and WDB1, XWDB1, WDB2, XWDB2 and so forth are write lines.
In the respective pairs of lines, RDB1 and XRDB1, RDB2 and XRDB2 and so forth, each pair transmits complementary signals which are 1-bit of read signal.
In the respective pairs of lines, WDB1 and XWDB1, WDB2 and XWDB2 and so forth, each pair transmits complementary signals which are 1-bit of write signal.
In FIG. 13, the read-only data bus and the write-only data bus are formed in a same metal layer and two lines of each pair are arranged adjacently to each other.
In FIG. 13, each line extends in the direction perpendicular to the sheet.
In this specification, the read line and write line in each Conventional Example and Embodiment are 1.5 xcexcm in thickness (width) and located at minimum 1.5 xcexcm intervals.
The write-only data bus and the read-only data bus are a 32 bits of complementary data bus and all lines are aligned within the bus width of 380 xcexcm.
The read-only data bus has 64 (32 pairs) read lines and the write-only data bus has 64 (32 pairs) write lines.
This allows stray capacitance between lines of each Conventional Example and Embodiment to be compared in the same conditions. The bus width of 380 xcexcm is calculated from the following equation:
1.5 xcexcmxc3x97{(64+64)+127}≈380 xcexcm
That is, 380 xcexcm is the narrowest bus width within which data buses are positioned in Conventional Examples 1 and 2.
While the demand for advanced micro-fabrication technique and high-performance semiconductor memory device grows, there has been a problem that performance of semiconductor memory device cannot be improved due to delay in working speed of data bus caused by increase in interference noise (including Miller noise) between read lines or write lines. The interference noise is generated by increase in wiring capacitance as well as coupling capacitance between lines.
As a conventional example, a semiconductor memory device having the structure that a write line and a read line are positioned alternately in a same layer is disclosed in patent publication for U.S. Pat. No. 2,508,245 (hereinafter referred to as Conventional Example 2). In this structure, in consideration that read data bus and write data bus do not operate concurrently, read lines and write lines are placed alternately, thereby to decrease interference noise such as Miller noise(caused by Miller capacitance)between read lines or write lines. This can achieve the semiconductor memory device with high-speed operating data bus.
With reference to FIGS. 1, 14 and 15, the DRAM of Conventional Example 2 will be described.
The semiconductor memory device of Conventional Example 2 has the same structure as that shown in FIG. 1. FIG. 1 has been already described above.
FIG. 14 is a schematic view illustrating data buses formed on the memory subarray of the semiconductor memory device according to Conventional Example 2 (when viewed from a top surface of the semiconductor memory device). In FIG. 14, reference numerals 1, 4 and 5 designate a memory subarray, a write-only data bus and a read-only data bus, respectively. The structure of these elements was explained referring to FIG. 1
FIG. 15 is a schematic sectional view illustrating wiring of data buses of the semiconductor memory device according to Conventional Example 2 (a sectional view taken along the face perpendicular to each line of data buses on the memory array (the face VIxe2x80x94VI of FIG. 14)).
As read lines RDB and XRDB and write lines WDB and XWDB are described referring to FIG. 13, their explanation will be omitted.
In FIG. 15, the read lines and the write lines are positioned alternately in a same metal layer. As shown in FIG. 15, in aligning data bus lines within the bus width of 380 xcexcm, an interval between a pair of lines (for example, RDB1 and XRDB1) becomes 4.5 xcexcm.
The stray capacitance between two lines in a pair depends on interval between the two lines except for a conductive part (width of a line intervening the two lines in a pair). Each line of data buses is in a precharged state during non-operating time. Therefore, an adjacent precharged line bus serves as a shield line between a pair of lines, thereby to eliminate any interference between the pair of lines. This can reduce interference noise such as Miller noise between read lines or write lines so that the semiconductor memory device can achieve high-speed operating data bus.
In order to operate the semiconductor memory device at higher speed, however, it is necessary to further reduce coupling capacitance and interference noise between read lines or write lines.
An objection of the present invention is to provide a semiconductor memory device that enables data buses to operate at high speed by reducing interference noise (including Miller noise) between data bus lines.
In semiconductor memories such as dual port RAM, write operation and read operation mix and a write-only data bus and a read-only data bus transmit a signal concurrently. In such semiconductor memories, interference noise between a write line and a read line also causes a problem. Another object of the present invention is to provide a semiconductor memory device such as dual port RAM which enables data buses to operate at high speed by reducing interference noise between a write line and a read line.
Further, given that write-only data bus becomes precharged at ground level and the write-only data bus is situated next to a VDD (power source) line, when dust generated during manufacturing process causes short-circuit between the write-only data bus and the VDD line, penetrating current between the GND (ground) line and the shorted VDD line occurs through the write-only data bus in precharged state, resulting in faulty penetrating current during standby.
In order to solve the above-mentioned problem, in the present invention, for instance, a read-only data bus and a VDD line are formed in one layer, a write-only data bus and a GND (VSS) line are formed in another layer, the read-only data bus become precharged at VDD level and the write-only data bus become precharged at GND level. This structure intends to provide a semiconductor memory device that causes no standby current failure even when short-circuit between adjacent lines occurs.
The present invention solves the above-described problem by means of the below-described configurations.
A semiconductor memory device according to an aspect of the present invention comprises a read-only data bus being formed in a first metal layer and having plural pairs of read lines precharged to an arbitrary voltage, two lines in a pair transmitting complementary read signals; and a write-only data bus being positioned in parallel with said read-only data bus, being formed in a second metal layer different from the first metal layer and having plural pairs of write lines precharged to an arbitrary voltage, two lines in a pair transmitting complementary write signals.
In the above-described semiconductor memory device according to another aspect of the present invention, the read-only data bus is formed on a memory array and transfers data amplified by a sense amplifier in a memory cell to peripheral circuit area; and the write-only data bus is formed on the memory array and transfers data from the peripheral circuit area to a memory cell.
In the above-described semiconductor memory device according to another aspect of the present invention, each two lines in a pair are positioned adjacent to each other and each line of the read-only data bus and each line of write-only data bus are arranged so as to substantially overlap one another in vertical direction.
In the above-described semiconductor memory device according to another aspect of the present invention, each two lines in a pair are positioned adjacent to each other and each line of the read-only data bus is arranged so as intervene between adjoining lines of the write-only data bus.
In the above-described semiconductor memory device according to another aspect of the present invention, two lines in a pair in the read-only data bus or the write-only data bus are positioned adjacent to each other, and interval between the two lines in a pair is narrower than interval between each two lines not in a pair.
In the above-described semiconductor memory device according to another aspect of the present invention, any ones of power source lines and ground lines are formed in a first metal layer and each line of them is arranged so as to intervene two lines not in a pair of the read-only data bus; and the other ones of power source lines and ground lines are formed in a second metal layer and each line of them is arranged so as to intervene two lines not in a pair of the write-only data bus.
In the above-described semiconductor memory device according to another aspect of the present invention, the read-only data bus is precharged to a same electrical potential as any ones of power source lines and ground lines formed in the first metal layer; and the write-only data bus is precharged to a same electrical potential as the other ones of power source lines and ground lines formed in the second metal layer.
A semiconductor memory device according to another aspect of the present invention, comprises a read-only data bus having plural pairs consisting of a first line and a second line precharged to an arbitrary voltage, two lines in a pair transmitting complementary read signals; and a write-only data bus being positioned in parallel with the read-only data bus and having plural pairs consisting of a third line and a fourth line precharged to an arbitrary voltage, two lines in a pair transmitting complementary write signals, wherein the first line and the third line are formed in a first metal layer, and the second line and the fourth line are formed in a second metal layer different from the first metal layer.
In the above-described semiconductor memory device according to another aspect of the present invention, the read-only data bus is formed on a memory array and transfers data amplified by a sense amplifier in a memory cell to peripheral circuit area; and the write-only data bus is formed on the memory array and transfers data from the peripheral circuit area to a memory cell.
In the above-described semiconductor memory device according to another aspect of the present invention, the first line and the third line are positioned alternately; the second line and the fourth line are positioned alternately; the second line in pair with the first line is arranged in substantially overlapping relation with the third line adjacent to the first line; and the fourth line in pair with the third line is arranged in substantially overlapping relation with the first line adjacent to the third line.
In the above-described semiconductor memory device according to another aspect of the present invention, interval between two lines in a pair of the read-only data bus is narrower than interval between two adjoining lines not in a pair of the read-only data bus, or interval between two lines in a pair of the write-only data bus is narrower than interval between two adjoining lines not in a pair of the write-only data bus.